The characteristics of semiconductor devices are often modeled in order to evaluate their reliability under different operating conditions. Typically, these tests are performed as a bench test in which an external device is coupled to an integrated circuit under test. The external device exercises one or more transistor devices on the integrated circuit with a time-varying AC stress signal. These bench tests often use a waveform generator for supplying the AC stress signal. After the transistor devices have been stressed at a predetermined temperature for a predetermined period of time, a different external device measures the resulting operating characteristics of the transistor device or devices under test.
For metal oxidize semiconductor (MOS) transistors, there are well-known MOS degradation mechanisms that occur only when a device is stressed with an AC applied bias. One degradation mechanism for P-channel (PMOS) devices is referred to as “Negative Bias Temperature Instability-induced Hot Carrier Injection” (NBT-HCI). In a CMOS inverter, oxide traps are formed by NBTI bias when the PMOS device in the inverter is in the linear region (when the inverter Vout is high and Vin is low). The traps are filled with hole charges when the PMOS device is off (when inverter Vout is low and inverter Vin is high). The charge traps enhance the electric field with each cycle and speed up degradation of the PMOS device. This mechanism is duty cycle dependent, so proof of existence requires the transistor device to be stressed under AC conditions with various duty cycles.
However, it is difficult to apply an AC stress signal to a MOS transistor in a bench system because the AC stress signal is modified by the parasitic inductance and capacitance of the test tool and the cables in the signal path that apply the AC stress signal to the device under test. It is difficult to be sure that the stress and measurement and setup is precise and that the signal applied to device under test is what is expected or desired.
Another test that is often performed on semiconductor devices is referred to as “burn-in”. For a burn-in test, the device under test is placed in an oven and heated to an elevated temperature and operated at a raised bias voltage. This is done to accelerate any latent failure mechanism to fail in days under accelerated conditions, rather than years under normal operating conditions. While at the elevated temperature and voltage, an AC stress signal is applied to the device, which stresses the device bias voltages. The device is exercised for a fixed amount of time or until a failure occurs. The cause of the failure can then be analyzed. Again, it is very difficult to apply an accurate AC bias signal to a device under test, particularly during a burn-in test. Another difficulty that arises with reliability test circuits is that the induced AC voltage or temperature stress that is applied to the device under test is also applied to the surrounding circuitry that delivers the drive signals and stress to the device. This further complicates the extraction of accurate model parameters and measurements and complicates the failure analysis of failing components.
Improved reliability test circuits are therefore desired. Various embodiments of the present invention address these problems, and offer other advantages over the prior art.